Vertical nano-size transistor on Si nanowire arrays.
Laboratory : LAAS-CNRS, Toulouse.
Semiconductor nanowires have quickly attracted the
interest of the scientific community thanks to their
remarkable properties in terms of elastic relaxation,
transport, electronic or optical confinement,. For
electronics, the gate-all-around nanowire device is the
ideal case for the electrostatic control of inversion charge
and thus an excellent candidate for ultimate transistors.
Vertical integration is a particularly attractive approach
because of its extreme density integration (NWs arrays)
and low cost fabrication method (no critical masks).
Furthermore, it is directly compatible with synthesized
NWs.
The objective of this thesis is to further develop a fabrication method of vertical silicon
nanowires by addressing the following key issues:
- The doping control in the NWs (homogeneous and junction).
- The definition and characterization of nanoscale contacts.
- Physical and electrical studies of gate dielectric (SiO2 plasma or high-K dielectric by ALD)
on vertical nanowires arrays.
This thesis, technology-oriented, allows the development of a wide knowledge (materials
science at the nanoscale, nanofabrication, physical and electrical characterization). The
knowledge gained in implementing these vertical structures in 3D can be exploited in other
applications such as (bio)-sensors-based nanowires, in which the detection sensitivity can be
significantly improved.
This thesis will take place in the LAAS-CNRS laboratory in Toulouse, which has a very
recent clean room facility (1500m ²) dedicated to the fabrication of micro / nano devices.
(http://www.laas.fr/laas09/2-27719-Home.php).
The candidate, MASTER graduated, will have good theoretical knowledge in materials
science and / or semiconductor physics and a taste for experimental work.
Contact F. Cristiano : cfuccio@laas.fr, G. Larrieu : guilhem.larrieu@isen.iemn.univ-lille1.fr
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